The trick to a more powerful computer chip? Going vertical.

Electrons typically flow through transistors in parallel to the chip surface, but what if the transistors were flipped sideways?
IBM vertical transport transistors

Flipping the individual transistors to sit vertically on the chip surface allows for more to fit. Connie Zhou for IBM

Modern computers and smartphones keep growing in capability, getting faster and more efficient with each model, and largely, that’s because the tiny microchips that power them have been evolving at an unprecedented rate. As Moore’s Law predicts, the number of transistors that an electronics-powering chip can hold is supposed to more or less double every two years. More transistors means speedier chips capable of performing more calculations, but achieving that without changing the size of the chips has computer engineers worried about running out of space. 

But IBM has a new approach: by rotating the individual transistors—the basic building blocks of chips that control or amplify electrical signals—to sit vertically on a chip instead of horizontally, engineers could pack a lot more of them into a given space.  

“Historically, transistors have been built to lie flat upon the surface of a semiconductor, with the electric current flowing laterally, or side-to-side, through them,” IBM said in a press release this week about a new chip architecture design that they’re also presenting tomorrow at the 2021 International Electron Devices meeting. “With new Vertical Transport Field Effect Transistors, or VTFET, IBM and Samsung have successfully implemented transistors that are built perpendicular to the surface of the chip with a vertical, or up-and-down, current flow.”  

To understand why this is potentially a big deal for semiconductor technology, it makes sense to first focus on individual transistors for a moment. “The DNA of any hardware technology is the transistor,” says Hemanth Jagannathan, a researcher at IBM. Billions of transistors can cover the surface of a silicon wafer, and these wafers are layered together to make a microchip

A typical, standard transistor that’s commonly found in electronics has three terminals: source, gate, drain. The current (which is a stream of electrons) flows from source to drain. The gates control the flow of currents and dictate the state of the transistor. When voltage is applied to the gate, the transistor is turned on and in state 1. When no current is flowing between the source and drain, the state is 0. Additionally, two separate transistors need a region in between to isolate them and prevent them from interfering with one another, and this is done with dummy gates. 

[Related: Understanding the global chip shortage, a big crisis involving tiny components]

Then there is a concept called “contacted gate pitch” which is the physical distance required to fit all the transistor components. “These are very basic structural requirements, and you can think of two hard walls and you have to fit the gate, the spacer, and the region for contact within that,” says Jagannathan. The walls keep closing in, but at some point, they can’t come any closer without sacrificing functionality.

Previous transistor innovations like FinFETs and nanosheets, have the gate, source, and drain on the same plane. With a vertical design, these structures essentially get stacked on top of each other, on the wafer. Plus, vertical transistors don’t need a dummy gate—they instead use something called shallow trench isolation, which conserves space. 

[Related: Intel to Mass-Produce New 3-D Transistors for Faster, More Efficient Computer Chips]

They also flip the orientation of the current flow, which still flows from the source to the drain, but now is perpendicular to the surface of the wafer instead of in parallel. 

“By doing this change, you now can independently change the gate length, spacer thickness, and the contacts,” Jagannathan says. “Because you’re able to go vertically and pack these transistors even closer together, you’re now able to get more transistors in a given area.”  

Huiming Bu, VP of hybrid cloud technology research at IBM, estimated that compared to today’s best 3D transistor technology (like FinFET), the VTFET can allow them to squeeze up to five times more transistors in a chip of the same size. This is useful in applications where the size of the chip is fixed. 

[Related: IBM’s latest quantum chip breaks the elusive 100-qubit barrier] 

In testing, compared to a FinFET device of the same scale, IBM claims to have observed a 50 percent reduction in capacitance and in resistance, which reduced power use by 85 percent. The team will continue to observe performance metrics like resistance in the device that determines how easily currents flow in and out, as well as how quickly the transistor can be turned off and on, and the isolation between the source and drain. 

Transistor design has been overhauled again and again over the last 80 years. The FinFET model improved upon a design called MOSFET from the 1960s. A few years ago, an architecture called a nanosheet with a gate all around the transistor made devices less leaky. 

“Semiconductor innovation is very hard,” says Bu. “It takes many years.” 

For example, he notes that High-K metal gates took 16 years to get to the manufacturing stage. FinFET, as another example, took the industry about 14 years to get to manufacturing. Nanosheet, which many groups are still tinkering with, has not reached the manufacturing stage yet, but is expected to in the next two years. After that, it will take about 14 more years until it’s introduced into everyday electronic devices. 

“We’re talking about [VTFET] today, not two years from now, because this innovation is such an important breakthrough,” says Bu. “We are asking the industry to look at this new technology offering and enable better processes, better design tools around this innovation, so our community can truly utilize this technology feature in five to eight years.”